This invention relates to power-on-reset circuitry, and more particularly, to power-on-reset circuitry with comparator-based trip point detectors for integrated circuits such as programmable logic device integrated circuits.
Integrated circuits are powered using power supply voltages. The power supply voltages may be supplied from an external source or may be derived from an external source using on-chip circuitry. Power-on-reset circuitry is used to control the power-on sequence for an integrated circuit.
Power-on-reset circuitry monitors the voltage associated with a given power supply. When the power supply attains a voltage within its normal operating range, the power-on-reset circuit generates an appropriate power-on-reset (POR) signal at its output. The state of the POR signal is indicative of the state of the power supply. When the power supply is not present or is below its normal operating range, the POR signal has one state, whereas when the power supply signal has risen to a valid level, the POR signal has another state. Use of the power-on-reset circuitry and associated POR signal ensures that sensitive logic circuitry does not commence operation before the power supply voltage is within its proper operating range. This helps to prevent errors that might otherwise arise from using an inadequate power supply.
Programmable logic devices and other integrated circuits are often powered using multiple power supply levels. The main processing circuitry on an integrated circuit, which is sometimes referred to as core circuitry or core logic, is often powered using a relatively low power supply voltage. Input-output circuitry is used to interface with external components and is often powered using a somewhat larger power supply voltage. In some integrated circuits, intermediate power supply voltages are used to power other blocks of circuitry.
Particularly in environments such as these, it can be difficult for power-on-reset circuitry to produce accurate power-on-reset signals. When multiple power supply voltages are involved, each power supply voltage may power up at a different time and may have a different operating voltage. This places a burden on the processing capabilities of the power-on-reset circuitry. Moreover, the relatively low core power supply voltages that are used on many integrated circuits are difficult to monitor accurately. Conventional power supply monitoring circuits are constructed from transistors with known threshold voltages. If the threshold voltages are accurately controlled, a signal can be generated that has one state when a power supply voltage trip point has not been exceeded and that has another state when the power supply voltage rises above the trip point. As core power supply voltages become lower and as transistor sizes shrink with advances in process technology, the ratio of transistor threshold voltage to core power supply voltage on an integrated circuit is becoming increasingly susceptible to process and temperature variations. These variations degrade the accuracy of conventional power-on-reset circuits.
It would therefore be desirable to be able to provide improved power-on-reset circuitry.